Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a construction of a static semiconductor memory device that can stably write and read data even under an operation condition of a low voltage.
Description of the Background Art
When transistor elements are miniaturized according to progress of miniaturization technology, voltage scaling according to the miniaturization is required from the viewpoint of reliability and power consumption of the elements. However, the miniaturization increases an influence on fluctuations in manufacturing parameters, so that a threshold voltage of transistors (insulated gate field effect transistor) forming memory cells is greatly varied, and an operation margin thereof lowers. Consequently, the semiconductor memory device cannot stably and reliably write and read data with a low power supply voltage.
Various constructions have been proposed for the purpose of stably writing and reading data even with a low power supply voltage.
A literature 1 (K. Zhang et al., “A 3-GHz 70 Mb SRAM in 65 nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” ISSCC 2005, Digest of Technical Papers, February 2005, pp. 474-475) discloses a construction in which a level of a memory cell power supply voltage is changed according to reading and writing of data for improving a static noise margin SNM and a write margin.
In Literature 1, a memory cell power supply voltage is controlled on a column-by-column basis, or in units of columns of memory cells. In a data write operation, the memory cell power supply voltage in a selected column is set to a low voltage of (VCC—LO), and the cell power supply voltages for the unselected columns are set to a slightly high voltage of (VCC—HI) similar to that in a read operation so that a static noise margin in the read operation is improved, and a write margin is ensured.
A literature 2 (M. Yamaoka et al., “Low-Power Embedded SRAM Modules with Expanded Margins for Writing,” ISSCC 2005, Digest of Technical Papers, February 2005, pp. 480-481) discloses a construction in which a memory cell power supply line in a selected column is set to a floating state in a data write operation, and the memory cell power supply lines in the other, unselected columns are kept at a predetermined voltage level similarly to that in a read operation. In Literature 2, a dummy bit line is employed for producing a word line deactivation timing signal WOFF according to a dummy bit line potential, and a word line driver is deactivated to drive a selected word line to an unselected state according to the dummy line potential.
In the construction disclosed in Literature 2, a discharging transistor setting a ground voltage level is provided for each word line separately from the word line driver. This discharging transistor is kept off in a standby state. When the selected word line is to be driven to an inactive state, the discharging transistor drives rapidly the word line to the unselected state with its large current driving power. After the word line is driven to the unselected state, the power supply to this word line driver is cut off so that a gate potential of the discharging transistor attains the L level according to the driver power supply voltage, and the discharging transistor is turned non-conductive.
A prior art reference 1 (Japanese Patent Laying-Open No. 2005-038557) discloses a construction in which a word line driver is formed using a level conversion circuit, and a selected word line is driven with an amplitude different from that of the memory cell power supply voltage. Prior Art Reference 1 also intends to improve write and read margins even when a threshold voltage of the memory cell transistor is varied, by converting the potential of the selected word line.
In the construction disclosed in Literature 1, the level of the memory cell power supply voltage is switched and controlled in units of memory cell columns, or on a column-by-column basis. Therefore, two kinds of voltages are required for the memory cell power supply voltage, which results in a problem that a power supply circuit becomes complicated for implementing the two-power-supply construction.
Although the memory cell power supply voltage can be switched, the switching voltage levels are fixed potentials produced by an internal power supply circuit. Therefore, even when variations occur in threshold voltage of the memory cell transistor due to fluctuations in process parameters, the switching voltage level does not change in close linkage with such variations, so that it is difficult to compensate for the changes in threshold voltage, and it is difficult to ensure reliably the write and read margins when changes occur in electric characteristics of the memory cell transistors such as threshold voltages.
In the construction disclosed in Literature 2, the memory cell power supply line in the selected column is set to the floating state in the data writing, and thereby the power supply voltage of the memory cells in the writing column, or write target column is lowered for insuring the write margin. In Literature 2, improvement of the write margin and reduction of the power consumption is discussed, but no consideration is given to the improvement of the read margin in the case where threshold voltages of the memory cell transistors are varied.
In the construction disclosed in Prior Art Reference 1, the memory cell transistor is formed using a Thin Film Transistor (TFT), and the level conversion circuit changes the potential amplitude of a selected word line for improving the write and read margins even when variations occur in threshold voltage of the memory cell transistors. Specifically, in Prior Art Reference 1, when the data writing is to be performed, the selected word line is driven to a potential level higher than the memory cell power supply potential, and a current driving power of the access transistors of the memory cell is increased so that fast writing is performed, and the write margin is ensured. In data reading, the selected word line is driven to a voltage level lower than a high-side power supply voltage of the memory cell. Thereby, the gate potential of the access transistors of the memory cell is lowered to lower their current driving power so that the static noise margin is ensured to prevent data destruction in the data read operation.
In the construction disclosed in the Prior Art Reference 1, however, the operation power supply voltage of the level conversion circuit is supplied separately and independently from the memory cell power supply voltage, and the shifted voltage level by the level conversion circuit is fixed and is not affected by the threshold voltage of the memory cell. In the Prior Art Reference 1, the power supply for the level shift must be arranged independently of and separately from the circuitry of the memory cell power supply, which complicates the construction of the power supply related circuitry. The potential of the selected word line is fixed, and therefore cannot flexibly follow the variations in threshold voltage of the memory cell transistors.
In the data write operation, the selected word line is driven to the level higher than that of the memory cell power supply, and no consideration is given to the stability of data of unselected memory cells that are connected to the selected row in the data writing.